Electronic calculator systems of the type wherein all of the main electronic functions are integrated in a single large cell integrated semiconductor chip or in a small number of such chips, are described in the following U.S. Patents, which are assigned the assignee of this invention:
U.S. Pat. No. 3,919,532 issued to Michael J. Cochran and Charles P. Grant on Nov. 11, 1975 and entitled "CALCULATOR SYSTEM HAVING AN EXCHANGE DATA MEMORY REGISTER".
U.S. Pat. No. 3,934,233 issued to Roger J. Fisher and Gerald D. Rogers on Jan. 20, 1976 and entitled "READ-ONLY-MEMORY FOR ELECTRONIC CALCULATOR".
U.S. Pat. No. 3,931,507 issued Jan. 6, 1976 to George L. Brantingham entitled "POWER-UP CLEAR IN AN ELECTRONIC DIGITAL CALCULATOR".
The concepts of these prior applications have made possible vast reductions in the cost of small personal-size calculators. Continuing efforts to reduce the cost of these products include the design of a single chip calculator system for use in large capacity calculators, such as scientific or business calculators. The chip disclosed herein may be utilized in scientific or business calculators for instance, because this chip has provisions for a number of storage registers, in addition to operational registers, as well as sufficient capacity to solve the more complicated mathematical expressions and functions used in scientific and business calculators including, for example, trigonometric and logarithmic relationships.
The present invention relates to a synchronous state counter of the type which may be used in an electronic calculator or microprocessor. An entire electronic calculator system, including the synchronous state counter of this invention, is disclosed. The electronic calculator disclosed is a serial, word organized calculator; however, it will be evident that the invention disclosed is not limited to that type calculator system. In the prior art, the state time counters were provided by, for instance, push/pull matrices of the type disclosed in U.S. Pat. No. 3,919,532. The push/pull matrix is preferably used with the sequentially addressed memory system or a shift register and provides an individual signal for each of the possible state times of the system. Thus for a calculator having 32 state times, for instance, 32 eight state time outputs would be provided by the state time generator of the prior art.
It is one object of this invention to provide a state counter which was not dependent upon a bit being shifted through either a sequentially addressed memory or a shift register. It is another object of this invention to provide a state counter providing the state outputs in binary format. It is yet another object of this invention to provide a synchronous state counter of simplified design, It is still yet another object of this invention to provide a synchronous state counter of expandable design.
The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, a synchronous state counter is provided on electronic calculator semiconductor chip for providing a binary indication of which one of the possible state times an electronic calculator is operating in. The state counter is responsive to an incrementing pulse provided once ech state time by the electronic calculator system. The state counter includes a plurality of latches for providing a binary representation of the number stored in the counter and a circuit associated with each one of the the latches for independently altering the state of the latch in response to a control signal. The control signal for the latch associated with the least significant bit of the number is provided by the incrementing pulse. The control signals for the latches storing bits more significantly than the least significant bit of the number are provided by control circuits responsive to the incrementing pulse and to the state of all latches storing bits less significant than the bit stored in the latch being controlled.